The present invention relates to a master slice type semiconductor integrated circuit, such as a gate array or an embedded array, and a method for manufacturing the same. More particularly, the present invention relates to improvements in making the effective use of wiring resources.
Master slice type semiconductor integrated circuits, such as, for example, gate arrays and embedded arrays, are manufactured using an unfinished wafer (master slice) in which those process steps to be performed before the metal wiring step are completed. The master slice is wired according to specific circuit functions required by the user and coated with a protection film, to thereby provide a finished wafer. Unfinished wafers may be stocked such that the delivery time is shortened to deliver semiconductor integrated circuits to customers.
Prior to manufacturing master slice type semiconductor integrated circuits, an unfinished wafer having basic cells arranged in a matrix is prepared in advance. Provision of through holes and placement and wiring of metal wiring layers to the unfinished wafer are automatically performed by an automatic placing and routing apparatus.
There is a growing tendency in which the number of metal wiring layers is increased, for example, from the two-layer to the three-layer and to the four-layer. The bottommost or first metal wiring layers in a semiconductor integrated circuit of the type described above are used as signal input wirings for inputting signals to gates of MOS transistors that form basic cells, power supply wirings for supplying power to sources thereof and signal output wirings for outputting signals from drains thereof, for example. These wirings are connected to the gates, sources or drains through contacts. Also, first metal wiring layers may be used as power source wirings for supplying power source voltages, such as potentials VDD and VSS, and signal wirings that provide connections within basic cells and between basic cells. Other metal wiring layers, such as second and third metal wiring layers, are used mainly as signal wirings.
Aluminum layers are generally used as metal wiring layers. For example, a two-layer metal wiring layer may include a first A1 wiring and a second A1 wiring. When wiring routes of the first and second A1 layers are determined by an automatic placing and routing apparatus, priority wiring directions are respectively assigned to the first and second A1 wirings.
It is noted that it is more difficult to miniaturize a master slice type semiconductor integrated circuit having a plurality of metal wiring layers compared to a standard cell type that is designed using basic cells registered in a library.
For example, let us consider one wiring example in which a signal wiring is externally lead out from a region between two power source wirings in the first layer (VDD, VSS) that are formed in a first priority wiring direction, for example. In this case, if the two power source wirings and the signal wiring are formed with the first layers, they are short-circuited. In order to cross over the power source wirings formed in the first priority wiring direction, the signal wiring has to be formed with a first layer signal wiring, a second layer signal wiring and a via that connects the first and second layer signal wirings. The second layer signal wiring is used only to cross over the first power source wiring. As a consequence, other wirings cannot be formed in such a region in the second layer. The other wirings in the second layer may need to take a detour. In this manner, the routing resource for the second layer is exhausted.
For the convenience of explanation, let us assume, for example, there are 100 lateral linesxc3x97100 vertical lines of lattice grids in a three-layer metal wiring structure, and the priority wiring direction for the first and third layers is the lateral direction and the priority wiring direction for the second layer is the vertical direction. In this case, while the first and third layers provide a total of 200 wiring lines in the lateral direction as the routing resource, the second layer provides 100 wiring lines in the vertical direction as the routing resource.
It is noted that the placement of the metal wirings in the first layer is mostly determined by the placement of basic cells, and the number of usable wiring lines is determined as a matter of course. Therefore, if the wirings in the second and third layers are disposed in a well-balanced manner, the size of the chip can reduced. However, as described above, if the wirings in the second layer are used to cross over the wirings in the first layer, the wiring efficiency of the second layer deteriorates.
In addition, when a roundabout routing of wirings is implemented by connecting a plurality of layers with vias, or a roundabout routing of wirings is made within the same layer, the wiring length increases. Moreover, in recent years, the line width has become narrower as the semiconductor manufacturing process has become more miniaturized. As a result, the resistance of the wiring per unit length tends to increase. Because of these two major factors, problems arise in that the wiring resistance is increased, and the signal delay is thus increased.
In solving these problems, the inventors of the present application have paid attention to the fact that the wiring resource of metal wiring layers and, in particular, the wiring resource of second metal wiring layers are not effectively utilized.
It is an object of the present invention to provide a master slice type semiconductor integrated circuit and a design method therefor that make an effective use of the wiring resource of metal wiring layers to thereby increase the wiring efficiency and reduce the chip size.
Another object of the present invention is to provide a master slice type semiconductor integrated circuit and a design method therefor that prevent the increase in the wiring resistance and reduce the signal delay as much as possible by making an effective use of the wiring resource of metal wiring layers to thereby increase the wiring efficiency.
In accordance with one embodiment of the present invention, a placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice having a plurality of basic cells formed in a matrix, in which first and second power source wirings that are formed along a first direction and traverse the plurality of basic cells are connected to a plurality of signal wirings that are formed along the first direction or a second direction that traverse the first direction to wire within each of the plurality of basic cells and/or between the plurality of basic cells.
The method according to the embodiment includes: the first step of registering in the automatic placing and routing apparatus that defines the first direction or the second direction as a priority wiring direction definitions of effective pin positions that connect the plurality of signal wirings, the plurality of first and second power source wirings and the plurality of basic cells for each of layers in which the wirings are formed; the second step of registering a net list that defines connections among the plurality of basic cells in the automatic placing and routing apparatus; and the third step of determining the placement of actual pin positions and wiring routes for the first and second power source wirings and the plurality of signal wirings based on data for the definitions of the effective pin positions and the net list.
The first step includes the step of defining the effective pin positions inside and outside of a region between the first power source wiring and the second power source wiring, in a region corresponding to one of a plurality of component layers with which transistors of the plurality of basic cells are formed and on lattice grids along which the plurality of basic cells are formed.
The third step includes the step of connecting one of the plurality of component layers and two of the plurality of signal wirings at the determined pin positions, in which two of the plurality of signal wirings are connected by the one component layer alone.
A semiconductor integrated circuit in which wirings are conducted in accordance with one embodiment of the present invention includes two contacts that connect one of a plurality of component layers with which transistors of a plurality of basic cells are formed and two of a plurality of signal wirings, wherein the two contacts are respectively disposed inside and outside of a region between a first power source wiring and a second power source wiring, and the two of the plurality of signal wirings are connected to one another by one of the component layers alone.
As a result, the signal wirings do not need to cross over the first and second power source wirings, and accordingly the wiring resource is effectively utilized. Also, the wiring length of the signal wirings is shortened as compared to a conventional structure in which signal lines cross over first and second power source wirings. Accordingly, one of the sources of signal delay can be eliminated. In accordance with one embodiment of the present invention, one of the component layers other than layers in which first and second power source wirings are disposed is used also as a wiring material to cross the signal wirings over the first and second power source wirings and connect them to one another.
In one embodiment, the one component layer may be a diffusion layer. If a Ti silicide is formed on a surface of the diffusion layer, the diffusion layer has a substantially low sheet resistance and can be used as a wiring material.
In this case, in the first step, a plurality of effective pin positions defined at positions on the diffusion layer may preferably be provided inside and outside the region between the first power source wiring and the second power source wiring. Further, in the first step, effective pin positions may be defined at all of the intersections of lattice grids on the diffusion layer. As a result, a wider range is secured in the selection of positions of contacts, and spaces are secured for passing signal wirings from other basic cells.
The basic cell includes a plurality of P-type transistors and a plurality of N-type transistors. The basic cell may be formed in a split-gate type in which a gate layer is provided for each of the plurality of P-type transistors and N-type transistors.
In this instance, in the first step, an effective pin position defined for each of the gate layers is provided in each of the areas inside and outside the region between the first power source wiring and the second power source wiring. As a result, for example, the gate of the P-type transistor is connected to the signal wiring in the area outside the region between the first power source wiring and the second power source wiring, and the gates of the P-type transistor and the N-type transistor can be connected in the area within the region.
The basic cell includes a plurality of P-type transistors and a plurality of N-type transistors. The basic cell may be formed in a common-gate type in which a common gate layer is provided for the plurality of P-type transistors and N-type transistors.
In this instance, in the first step, an effective pin position defined for each of the common gate layers is provided in an area inside the region between the first power source wiring and the second power source wiring, and another effective pin position is provided at each end of the common gate layer outside the region.
As a result, for example, a signal wiring to the first gate or the second gate can be connected to a contact that is disposed outside the region between the first and second power source wirings, and a signal wiring that crosses over the first and second power source wirings is not required.
In a placing and routing method in accordance with another embodiment of the present invention, the first step includes the step of defining the effective pin positions inside and outside a region between the first power source wiring and the second power source wiring, in a region corresponding to a gate layer of each of transistors that form the plurality of basic cells and on lattice grids along which the plurality of basic cells are disposed.
A master slice type semiconductor integrated circuit designed according to the method has:
a substrate having a plurality of basic cells formed in a matrix thereon,
first and second power source wirings that are formed along a first direction and traverse the plurality of basic cells,
a plurality of signal wirings that are formed along the first direction or a second direction that traverses the first direction to provide connections within each of the plurality of basic cells and/or between the plurality of basic cells, and
a contact that connects one of gate layers of transistors that form one of the plurality of basic cells to one of the plurality of signal wirings in an area outside a region between the first power source wiring and the second power source wiring.
In accordance with the method and the circuit designed by the method, one of the gate layers of transistors that form one of the plurality of basic cells can be connected to one of the plurality of signal wirings by a contact disposed outside the region between the first power source wiring and the second power source wiring. In this case, a signal wiring to the gate can be connected to the contact that is disposed outside the region between the first power source wiring and the second power source wiring, and therefore a signal wiring that crosses over the first and second power source wirings is not required.